2017-06-18 15:52:59 UTC
As some of you may know, I’m part of the x86 porting project, and I’m responsible for some very low-level (close to the hardware) aspects of the OS. For the past year-and-a-half, I’ve been working on the design for the SWIS (Software Interrupt Services) layer for X86; full-time for some months in the beginning and end, part-time for about a year while I was mostly focused on the Java 8 port with Brett.
For those who don’t know what SWIS is, it’s a piece of software that was designed as part of porting VMS to Itanium, that provides VAX- and Alpha-like mechanisms that are not natively available on the hardware to the rest of the operating system; it’s partly a replacement for the PALcode on Alpha, partly a replacement for hardware mechanisms built into Alpha. The main features it provides the rest of the OS with are 32 IPL levels, prioritization of hardware interrupts to the 16 high IPL levels, and software interrupts tied to the 16 low IPL levels, as well as ASTs for each of the four modes.
On x86, SWIS will be partly responsible for more VAX- and Alpha-like features, like the 4 modes we’re used to, each with their own page protections. (The X86 hardware provides us only with two useable rings).
A couple of weeks ago, shortly after completing a first draft of the SWIS design, I spent two weeks at the headquarters in Bolton (I'm based in the Netherlands, and usually work from home). During this two-week visit, I was fortunate to have Burns Fisher - Digital/Compaq/VSI alumnus and architect of the SWIS layer on Itanium - brought in as a consultant for several days. During those days, we went through the design with a very fine tooth comb. We did find a flaw in the design, one that would have made it possible for user-mode code to exhaust the kernel stack, bringing the system down with a kernel-stack invalid bug check, and we found a few places where more clarification was in order.
Following that, we organized a design review meeting with most of the X86 team, where we presented the finished design. I plan to offer a simplified version of that presentation at boot camp.
The design being reviewed and approved, I have began implementing the SWIS layer. The first item that has been implemented is a primitive exception handler that can be used at boot time; Paul Jacobi is working to give us debugging capabilities very early on in SYSBOOT that uses this primitive handler.
Further parts of the implementation will include emulation of VAX/Alpha-like internal processor registers (MFPR/MTPR instructions), full-fledged exception, interrupt and machine check handling, system service dispatching, software interrupts, ASTs, context switching and scheduling, and the bootstrapping and initialization of all of the above.
Let me know if you have any questions, and please be aware that if we don’t seem to be around here very often, it’s possibly because we’re very hard at work actually building something.